Design of 4 : 1 Multiplexer using With-Select Concurrent Statement (VHDL Code).

Design of 4 : 1 Multiplexer using with-select Concurrent Statement (Data Flow Modeling Style)-

Output Waveform : 4 :  1 Multiplexer

Program-


-------------------------------------------------------------------------------
--
-- Title       : multiplexer_4_1
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : multiplexer using with select.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer_4_1 is
     port(
         din : in STD_LOGIC_VECTOR(3 downto 0);
         sel : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC
         );
end multiplexer_4_1;

architecture multiplexer4_1_arc of multiplexer_4_1 is
begin

    with sel select
    dout <= din(3) when "00",
            din(2) when "01",
            din(1) when "10",
            din(0) when others;

end multiplexer4_1_arc;