Design of 2 : 4 Decoder using With-Select Concurrent Statement (VHDL Code).

Design of 2 : 4 Decoder using With-Select Concurrent Statement (Data Flow Modeling Style)-

Output Waveform : 2 : 4 Decoder

VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : decoder2_4
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 2 : 4 Decoder using with select.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is
     port(
         din : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end decoder2_4;

architecture decoder2_4_arc of decoder2_4 is
begin

    with din select
    dout <= "1000" when "00",
            "0100" when "01",
            "0010" when "10",
            "0001" when others;

end decoder2_4_arc;