Design of SR - Latch using Behavior Modeling Style (VHDL Code).

Design of SR - Latch using Behavior Modeling Style -

Output Waveform :  SR (Set-Reset Latch)

VHDL Code -




-------------------------------------------------------------------------------
--
-- Title       : SR_Latch
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : Set Reset (SR) Latch using Behavior Modeling Style.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity SR_Latch is
     port(
         enable : in STD_LOGIC;
         s : in STD_LOGIC;
         r : in STD_LOGIC;
         reset : in STD_LOGIC;
         q : out STD_LOGIC;
         qb : out STD_LOGIC
         );
end SR_Latch;

architecture SR_Latch_arc of SR_Latch is
begin

    latch : process (s,r,enable,reset) is
    begin
        if (reset='1') then
            q <= '0';
            qb <= '1';
        elsif (enable='1') then
            if (s/=r) then
                q <= s;
                qb <= r;
            elsif (s='1' and r='1') then
                q <= 'Z';
                qb <= 'Z';
            end if;
        end if;
    end process latch;

end SR_Latch_arc;