VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide] - Part ii

 

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This is the Part ii of last Video "VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]", for deeper understanding, and it is very important to have deeper insights on Sequential and Concurrent statement, if you are designing anything in VHDL or Verilog HDL. In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach. Now dig down little more with an example - Here I written two architectures with identical statements, top left architecture will execute those statements concurrently, but bottom right architecture will execute statements sequentially. Here if you noticed that in both the statements the output signal is same, that is Dout. And we are saying Dout gets the value of logical AND of inputs and in the second statement we says Dout gets the value of logical OR of inputs.

architecture Concurrent of my_design is begin Dout <= A AND B ; Dout <= A OR B; end Concurrent; --------------------------------------------- architecture Sequential of my_design is begin process (A,B,C) begin Dout <= A AND B ; Dout <= A OR B; end process; end Sequential;

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Do you see any problem in this structure ? If your answer is No, than try to figure out the output if input A is ‘0’ and input ‘B’ is 1, so the output of the AND gate is digital ‘0’ and the output of the OR gate is digital ‘1’, and you shorted them both these outputs. This is not good for the hardware, right? This is called contention, because two set of logics are driving the same signal and this is not allowed to synthesized as well, so You will not be able to synthesized your design, and you will probably get the synthesizer error in such cases. Now let’s talk about the sequential statements – Here we have the same set of statements, but these are now executing sequentially, means 1st statement executes first which says Output Dout gets the value of logical AND of inputs. So we made a AND gate. Now execute the 2nd statement which says Output Dout gets the value of logical OR of inputs. So here this second statement override the output signal Dout. Which means at the end of this statement Dout has the value of OR function. And the first statement of AND function get’s ignore completely. And we will get the only functionality of OR gate.

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