Design of Frequency Divider (Divide by 10) using Behavior Modeling Style (VHDL Code).

Design of Frequency Divider  (Divide by 10) using Behavior Modeling Style -

Output Waveform :    Frequency Divider (Divide by 10) .

VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_by10
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : frequency divider by 10.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity frequency_divider_by10 is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_by10;


architecture frequency_divider_by10_arc of frequency_divider_by10 is
begin

    divider : process (clk) is
    variable m : integer range 0 to 15 := 0;
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
       
        if (m=10) then
            m := 0;
        end if;
       
        if (m<5) then
            out_clk <= '1';
        else
            out_clk <= '0';
        end if;
    end process divider;

end frequency_divider_by10_arc;