Design of 4 Bit Serial IN - Serial OUT Shift Register using Behavior Modeling Style-
 |
| Output Waveform : Serial IN - Serial OUT Shift Register |
VHDL Code-
-------------------------------------------------------------------------------
--
-- Title : siso_behavior
-- Design : vhdl_upload 1
-- Author : Naresh Singh Dobal
-- Company : nsd
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File : serial in serial out shift register using behavior modeling style.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity siso_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end siso_behavior;
architecture siso_behavior_arc of siso_behavior is
begin
siso : process (clk,din,reset) is
variable s : std_logic_vector(3 downto 0) := "0000" ;
begin
if (reset='1') then
s := "0000";
elsif (rising_edge (clk)) then
s := (din & s(3 downto 1));
dout <= s(0);
end if;
end process siso;
end siso_behavior_arc;
i want using structural modelling in our college
ReplyDeletewe want using dataflow
ReplyDeletejai hind
ReplyDeletelibrary ieee;
ReplyDeleteuse ieee.std_logic_1164.all;
Entity D_FF1_Tb is
end D_FF1_Tb;
architecture D_FF1_Tb_Arc of D_FF1_Tb is
component D_FF1 is
port(
Clk : in bit;
Rst : in bit;
Ce: in bit;
d: in bit;
q: out bit;
qn: out bit
);
end component;
signal Clk: bit;
signal Rst: bit;
signal Ce: bit;
signal d: bit;
signal q: bit;
signal qn: bit;
begin
inst_ABC: D_FF1 port map(Clk,Rst,Ce,d,q,qn);
process
begin
Clk<='0'; wait for 10 ns;
Clk<='1'; wait for 10 ns;
end process;
process
begin
Ce<='1'; wait for 50 ns;
Ce<='0'; wait for 50 ns;
end process;
process
begin
rst<='0'; wait for 100 ns;
rst<='1'; wait for 100 ns;
end process;
process
begin
d<='0' ; wait for 20 ns;
d<='1' ;wait for 20 ns;
end process;
end D_FF1_Tb_Arc;
shouldnt the dout assignment be put after endind the if statement and before ending the process statement
ReplyDelete