Design of Toggle Flip Flop using Behavior Modeling Style -
 |
| Output Waveform : Toggle Flip Flop |
VHDL Code -
-------------------------------------------------------------------------------
--
-- Title : Toggle_flip_flop
-- Design : vhdl_upload 1
-- Author : Naresh Singh Dobal
-- Company : nsd
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File : Toggle Flip Flop using Behavior modeling Style.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Toggle_flip_flop is
port(
t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end Toggle_flip_flop;
architecture toggle_flip_flop_arc of Toggle_flip_flop is
begin
tff : process (t,clk,reset) is
variable m : std_logic := '0';
begin
if (reset='1') then
m := '0';
elsif (rising_edge (clk)) then
if (t='1') then
m := not m;
end if;
end if;
dout <= m;
end process tff;
end toggle_flip_flop_arc;
what will happen when clk =0 ?
ReplyDeleteentity jkfff is
ReplyDeletePort ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : inout STD_LOGIC);
end jkfff;
architecture Behavioral of jkfff is
begin
process(j,k,clk,rst)is
begin
if(rst='1')then
q <= '0';
elsif(j/=k and rising_edge(clk))then
q<=j;
elsif (j='1' and k='1' and clk='1') then
q<= not q;
elsif(j='0' and k='0' and clk='1') then
elsif(j/=k and clk='0')then
q<=q;
elsif (j='1' and k='1' and clk='0') then
q<= q;
elsif(j='0' and k='0' and clk='0') then
q<= q;
end if;
end process;
ReplyDeletelibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity t_ff is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end t_ff;
architecture Behavioral of t_ff is
signal s : std_logic;
begin
process(clk,reset)
begin
if (reset = '1') then
s <= '0';
elsif (clk'event and clk = '1' ) then
if ( t = '1') then
s <= not s;
else
s <= s;
end if;
q <= s;
end if;
end process;
end Behavioral;