Design of 2 Bit Comparator Using When-Else Statement (VHDL Code).

Design of 2 Bit Comparator Using When-Else Statement (Data Flow Modeling Style)-

Output Waveform  :  2 Bit Comparator

VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : comparator_2bit
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 2 Bit Comparator Design.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator_2bit is
     port(
         a : in STD_LOGIC_VECTOR(1 downto 0);
         b : in STD_LOGIC_VECTOR(1 downto 0);
         equal : out STD_LOGIC;
         greater : out STD_LOGIC;
         lower : out STD_LOGIC
         );
end comparator_2bit;

architecture comparator_2bit_arc of comparator_2bit is   
begin

    equal <= '1' when (a=b) else
             '0';
           
    greater <= '1' when (a<b) else
               '0';
   
    lower <= '1' when (a>b) else
             '0';
       

end comparator_2bit_arc;