Design of Frequency Divider (Divide by 8) using Behavior Modeling Style (VHDL Code).

Design of Frequency Divider (Divide by 8) using Behavior Modeling Style -

Output Waveform :   Frequency Divider (Divide by 8).

VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_by8
-- Design      : vhdl_upload2
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : frequency divider by 8.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_divider_by8 is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_by8;


architecture frequency_divider_by8 of frequency_divider_by8 is
begin

    divider : process (clk) is
    variable m : std_logic_vector (2 downto 0) := "000";
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        out_clk <= m(2);
    end process divider;

end frequency_divider_by8;