Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) (VHDL Code).

Design of 4 Bit Subtractor using Loops (Behavior Modeling Style).

Output Waveform :  4 Bit Subtractor

VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : subtractor_4bit
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : 4 bit subtractor using loops.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity subtractor_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         diff : out STD_LOGIC_VECTOR(3 downto 0)
         );
end subtractor_4bit;


architecture subtractor_4bit_loop of subtractor_4bit is
begin

    sub4 : process (a,b) is
    variable l : std_logic_vector (3 downto 0) ;
    variable s : std_logic_vector (4 downto 0) ;
    begin
        l := not b;
        s(0) := '1';
        for i in 0 to 3 loop
            diff(i) <= a(i) xor l(i) xor s(i);
            s(i+1) := (a(i) and l(i)) or (l(i) and s(i)) or (s(i) and a(i));
        end loop;
    end process sub4;

end subtractor_4bit_loop;