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Saturday, July 20, 2013

Design of 2 to 4 Decoder using IF-ELSE Statement (VHDL Code).





Design of 2 to 4 DECODER using IF-ELSE Statements (Behavior Modeling Style).


Output Waveform :   2 to 4 Decoder



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : decoder2_4
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
-------------------------------------------------------------------------------
--
-- File        : 2 to 4 decoder using if else.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is
     port(
         din : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end decoder2_4;


architecture decoder2_4_arc of decoder2_4 is
begin

    encoder : process (din) is
    begin
        if (din="00") then
            dout <= "1000";
        elsif (din="01") then
            dout <= "0100";
        elsif (din="10") then
            dout <= "0010";
        else
            dout <= "0001";
        end if;
    end process encoder;    

end decoder2_4_arc;
 

4 comments:

  1. sir please will u give the code for 1 out of n decoder in vhdl

    ReplyDelete
  2. Please, change the encoder word to decoder in process statement of 2:4 decoder using if else statement.

    ReplyDelete
  3. sir, did you use quatus 2 version 9.1 or version 11?

    ReplyDelete
  4. module dec2to4 (W, En, Y);
    input [1:0]W;
    input En;
    output reg [0:3] Y;
    integer k;
    always @(W, k)
    for (k = 0; k < = 3; k = k+1)
    if (W == k)
    Y[k] = En;
    endmodule
    help me find error

    ReplyDelete