Design of 4 Bit Adder / Subtractor using XOR Gate and Full Adder (Structural Modeling Style) (VHDL Code).

Design of 4 Bit Adder / Subtractor using XOR Gate and Full Adder (Structural Modeling Style) -

Output Waveform  :   4 Bit Adder / Subtractor Design

VHDL Code -




-------------------------------------------------------------------------------
--
-- Title       : adder_4bit
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 4 Bit Adder / Subtractor Design using Structural Modeling Style.vhd




library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_subtractor_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         sel : in STD_LOGIC;
         sum : out STD_LOGIC_VECTOR(3 downto 0)
         );
end adder_subtractor_4bit;

architecture adder_4bit_arc of adder_subtractor_4bit is

Component fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end component;       

signal s : std_logic_vector (2 downto 0);
signal l : std_logic_vector (3 downto 0);


begin        
   
    l <= b xor (sel & sel & sel & sel);
   
    u0 : fa port map (a(0),l(0),sel,sum(0),s(0));
    u1 : fa port map (a(1),l(1),s(0),sum(1),s(1));
    u2 : fa port map (a(2),l(2),s(1),sum(2),s(2));
    ue : fa port map (a(3),l(3),s(2),sum(3),open);

end adder_4bit_arc;           







---------------- Full Adder Design ----------------------




library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end fa;

architecture fa_arc of fa is
begin
   
    sum <= a xor b xor c;
    carry <= (a and b) or (b and c) or (c and a);
   
end fa_arc;