Design of a Simple numbers based Grading System using Behavior Modeling Style (VHDL Code).

Design of a Simple Number Based Grading System using CASE Statements (Behavior Modeling Style)-

Output Waveform : Grading Systems

VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : grading_system
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : Grading system design using case statements.vhd       
   
   
  library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity grade is
     port(
         din : in std_logic_vector (6 downto 0);
         d : out STD_LOGIC;   
         f : out std_logic ;
         a : out STD_LOGIC;
         b : out STD_LOGIC;
         c : out STD_LOGIC;
         e : out STD_LOGIC
         );
end grade;


architecture grade_arc of grade is      
signal number : integer ;
begin                 
    number <= conv_integer (din);
    p0 : process (din)
    begin              
       
        a <= '0';
        b <= '0';
        c <= '0';
        d <= '0';
        e <= '0';
        f <= '0';
        case number is
            when 33 to 40 => e <= '1';
            when 41 to 45 | 46 to 50 => d <= '1';
            when 51 to 60 => c <= '1';
            when 61 to 70 => b <= '1';
            when 71 to 100 => a <= '1';
            when others => f<= '1';
        end case;
    end process;

end grade_arc;