Design of 4 Bit Adder cum Subtractor using Structural Modeling Style (VHDL Code).

Design of 4 Bit Adder cum Subtractor using Structural Modeling Style -

Output Waveform  :   4 Bit adder / subtractor Design

VHDL Code-



-------------------------------------------------------------------------------
--
-- Title       : adder_subtractor_4bit
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of 4 Bit Adder cum Subtractor using structural modeling style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_subtractor_4bit is
     port(
         sel : in STD_LOGIC;
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end adder_subtractor_4bit;

architecture adder_subtractor_4bit_arc of adder_subtractor_4bit is

component adder_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         carry : out STD_LOGIC;
         sum : out STD_LOGIC_VECTOR(3 downto 0)
         );
end component;      

component subtractor_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         borrow : out STD_LOGIC;
         diff : out STD_LOGIC_VECTOR(3 downto 0)
         );
end component;               

component mux is
     port(
         sel : in STD_LOGIC;
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end component;            

signal m : std_logic_vector (3 downto 0);
signal n : std_logic_vector (3 downto 0);

begin           
   
    u0 : adder_4bit port map (a,b,open,m);
    u1 : subtractor_4bit port map (a,b,open,n);
    u2 : mux port map (sel,m,n,dout);

end adder_subtractor_4bit_arc;   



-------------------  4   Bit   Adder Design -----------------
 


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         carry : out STD_LOGIC;
         sum : out STD_LOGIC_VECTOR(3 downto 0)
         );
end adder_4bit;

architecture adder_4bit_arc of adder_4bit is

Component fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end component;       

signal s : std_logic_vector (2 downto 0);

begin
   
    u0 : fa port map (a(0),b(0),'0',sum(0),s(0));
    u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
    u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
    ue : fa port map (a(3),b(3),s(2),sum(3),carry);

end adder_4bit_arc;       



-----------------  4 Bit Subtractor Design ---------------



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity subtractor_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         borrow : out STD_LOGIC;
         diff : out STD_LOGIC_VECTOR(3 downto 0)
         );
end subtractor_4bit;

architecture subtractor_4bit_arc of subtractor_4bit is   

Component fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end component;       

signal s : std_logic_vector (2 downto 0);
signal l : std_logic_vector (3 downto 0);

begin   
   
    l <= not b;
   
    u0 : fa port map (a(0),l(0),'1',diff(0),s(0));
    u1 : fa port map (a(1),l(1),s(0),diff(1),s(1));
    u2 : fa port map (a(2),l(2),s(1),diff(2),s(2));
    ue : fa port map (a(3),l(3),s(2),diff(3),borrow);     
   

end subtractor_4bit_arc;           




---------------- Full Adder Design ----------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end fa;

architecture fa_arc of fa is

begin
   
    sum <= a xor b xor c;
    carry <= (a and b) or (b and c) or (c and a);
   
end fa_arc;


------------- 2 : 1 Multiplexer Design (4 Bit).. --------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux is
     port(
         sel : in STD_LOGIC;
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end mux;

architecture mux_arc of mux is
begin

    with sel select
    dout <= a when '0',
    b when others;

end mux_arc;