Design of First IN - First OUT (FIFO) Register using Behavior Modeling Style (VHDL Code).

Design of First IN - First OUT  (FIFO)  Register using Behavior Modeling Style -

Output Waveform :   First IN - First OUT (FIFO) Register.

VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : FIFO
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of First In - First OUT Register.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FIFO is
     port(
         en : in STD_LOGIC;
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end FIFO;


architecture FIFO_arc of FIFO is
begin                   
   
    fifo_design : process (en,clk,din) is
    variable mem : std_logic_vector (3 downto 0) := (others => '0');
    begin
        if (en='1') then
            if (rising_edge (clk)) then
                dout <= mem(0);
                mem := (din & mem(3 downto 1));
            end if ;
        end if;
    end process fifo_design;
   

end FIFO_arc;