Design of Frequency Divider Module (Divide by 2) using Behavior Modeling Style (VHDL Code).

Design of Frequency Divider Module (Divide by 2) using Behavior Modeling Style -

Output Waveform :   Frequency Divider (divide by 2).

VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_by2
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Frequency Divder by 2.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity frequency_divider_by2 is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_by2;


architecture frequency_divider_by2_arc of frequency_divider_by2 is
begin

    divider : process (clk) is
    variable m : std_logic := '0';
    begin
        if (rising_edge (clk)) then
            m := not m;
        end if;
        out_clk <= m;
    end process divider;
   
end frequency_divider_by2_arc;