Saturday, 20 July 2013

Design of SR Flip Flop using Behavior Modeling Style (VHDL Code).

Design of SR Flip Flop using Behavior Modeling Style - Output Waveform :   SR (Set - Reset)  Flip Flop

VHDL Code -

-------------------------------------------------------------------------------
--
-- Title       : sr_flip_flop
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsd
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : SR Flip Flop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sr_flip_flop is
port(
s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
);
end sr_flip_flop;

architecture sr_flip_flop_arc of sr_flip_flop is
begin

srff : process (s,r,clk,reset) is
begin
if (reset='1') then
q <= '0';
qb <= '1';
elsif (rising_edge (clk)) then
if (s/=r) then
q <= s;
qb <= r;
elsif (s='1' and r='1') then
q <= 'Z';
qb <= 'Z';
end if;
end if;
end process srff;

end sr_flip_flop_arc; Anonymous said...

Thank you! This helped me very much! Anonymous said...

Thank u so much!!!

pravesh dhyani said...

what this command means "if (s/=r) then" ?

asrofi lazuardi said...

@pravesh_dhayani : its mean "s not equivalent r"

arghya dhar said...

what is the use of z here ? Anonymous said...

Output is always coming as q=0 and qb=1

nitesh kumar said...

what about s='0' ans r='0'?

Unknown said...

Q=qn (previous state )