Tuesday, 16 July 2013

Design of 2 to 1 Multiplexer using Structural Modeling Style (VHDL Code).




Design of   2   to   1     Multiplexer using Component Declaration & Instance Calling   (Structural Modeling Style).




Output Waveform :  2 to 1 Multiplexer
VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : multiplexer2_1
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of 2 to 1 multiplexer using Structural Modeling Style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer2_1 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         sel : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end multiplexer2_1;

architecture multiplexer2_1_arc of multiplexer2_1 is   
component and2 is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          dout : out STD_LOGIC
          );
end component and2;   

component or2 is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          dout : out STD_LOGIC
          );
end component or2;   

component not1 is
    port (a : in STD_LOGIC;   
          dout : out STD_LOGIC
          );
end component not1;   

signal m : std_logic;
signal n : std_logic;
signal o : std_logic;


begin   
   
    u0 : and2 port map (a,m,n);
    u1 : and2 port map (sel,b,o);
    u2 : or2 port map (n,o,dout);
    u3 : not1 port map (sel,m);
   

end multiplexer2_1_arc;      



---------------- AND Gate Design ----------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and2 is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          dout : out STD_LOGIC
          );
end and2;

architecture and2_arc of and2 is
begin
   
    dout <= a and b;
   
end and2_arc;



---------------- OR Gate Design ----------------------



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity or2 is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          dout : out STD_LOGIC
          );
end or2;

architecture or2_arc of or2 is
begin
   
    dout <= a or b;
   
end or2_arc;   



---------------- Not Gate Design ----------------------





library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity not1 is
    port (a : in STD_LOGIC;   
          dout : out STD_LOGIC
          );
end not1;

architecture not1_arc of not1 is
begin
   
    dout <= not a ;
   
end not1_arc;

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