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Tuesday, November 19, 2013

VHDL Lab Exercise ::: Exercise 2






VHDL Lab Exercise   :::   Exercise 2 -

LAB2 : COMBINATIONAL SYSTEM DESIGN USING DATA FLOW MODELLING STYLE.
Lab Exercise 2a :: VHDL with Naresh Singh Dobal Learning Series.
Lab Exercise 2-b :: VHDL with Naresh Singh Dobal Learning Series.


Task1 :      Write a VHDL code for all gates using with-select.
Task2:       Write a VHDL code for Full adder using with-select.
Task3:       Write a VHDL code for Full subtractor using with-select. .
Task4:       Write a VHDL code for 4:1 Multiplexer using With-select.
Task5:       Write a VHDL code for a 1:4 Demultiplexer using with-select.
Task6:       Write a VHDL code for a 8:3 Encoder using With-Select.
Task7:       Write a VHDL code for a 3:8 Decoder using With-Select.
Task8 :      Write a VHDL code for all gates using when-else.
Task9:       Write a VHDL code for Full adder using when-else.
Task10:     Write a VHDL code for Full subtractor using when-else.
Task11:     Write a VHDL code for 4:1 Multiplexer using When-else. .
Task12:     Write a VHDL code for a 1:4 Demultiplexer using when-else.
Task13:     Write a VHDL code for a 8:3 Encoder using When-else.
Task14:     Write a VHDL code for a 3:8 Decoder using When-else.
Task15:     Write a VHDL code for 8:3 Encoder with Priority using when-else.
Task16:     Write a VHDL code for BINARY to GRAY Converter using with-select.
Task17:     Write a VHDL code for GRAY to BINARY Converter using with-select.
Task18:     Write a VHDL code for BINARY to GRAY Converter using when-else.
Task19:     Write a VHDL code for GRAY to BINARY Converter using when-else.
Task20:     Write a VHDL code for BINARY to EXCESS-3 using With-select.
Task21:     Write a VHDL code for BINARY TO GRAY Converter using equation.
Task22:     Write a VHDL code for GRAY to BINARY Converter using equations.
Task23:    Write a VHDL code for BINARY TO EXCESS-3 using equations.

If you feel any difficulties in any assignment then follow the below link...

Solutions for problems in with-select statements.
Solution for problems in when-else statements.


I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com
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VHDL Lab Exercise :: Exercise 1






VHDL Lab Exercise   :::   Exercise 1 -


LAB 1:  COMBINATIONAL SYSTEM DESIGN USING BASIC GATES AND EQUATIONS.
VHDL Lab Exercise 1 :: VHDL with Naresh Singh Dobal Learning Series.


Task1 :   Write a VHDL Program for all Logic Gates.
Task2 :   Write a VHDL code for a Half Adder using Digital Electronics.
Task3 :   Write a VHDL code for a Full Adder using Digital Electronics.
Task4 :   Write a VHDL code for a Half Subtractor using Digital Electronics.
Task5 :   Write a VHDL code for a Full Subtractor using Digital Electronics.
Task6:    Write a VHDL code for a 4:1 Multiplexer using Digital Electronics.
Task7:    Write a VHDL code for a 1:4 Multiplexer using Digital Electronics.
Task8:    Write a VHDL code for a 4:2 Encoder using Digital Electronics.
Task9:    Write a VHDL code for a 2:4 Decoder using Digital Electronics.
Task10:  Write a VHDL code for 1 bit Comparator using Digital Electronics. 


If you feel any difficulties in any assignment then follow the below link...

Solutions of assignment paper 1.


I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact me at nsdobal@gmail.com

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Tuesday, November 12, 2013

A Small Discussion about VHDL & Verilog HDL...






A Small Discussion about VHDL & Verilog HDL -


VHDL or Verilog HDL - A small discussion (VHDL with Naresh Singh Dobal learning Series).



Verilog HDL is easier to understand and use, It is very effectively used for simulation and synthesis. but it lacks for system level or complex designing. It is promoted by OVI (Open Verilog International). It is widely used for ASIC designing or lower level design (RTL or  lower), but this results in faster simulation and effective synthesis. Mostly used in North America, Asia & Japan, but not popular in Europe.

As comparable to verilog HDL, VHDL is more complex, thus difficult to learn and use. But this offers more flexibility of designing. Since VHDL is better suited for handling very complex systems, so it is now gaining popularity. VHDL  is mainly promoted by VHDL international. VHDL is relatively weaker in lower designs. But superior in system level design. Many believes that in long terms presents better condition and adaptability than its competitors. This language is widely used in Europe, significantly used in US and Canada, but this disliked in Japan...


Both the HDL's are used to describe electronic systems.
The function of systems is to get input data from it's environment and give output some data in return.
In verilog HDL this is called a module which is a basic building block in Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.
 Both the Languages are IEEE Standard.


I would love to read your suggestions and comments here below,
Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com

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Monday, November 11, 2013

Basics of VHDL Language Execution process concurrent and sequential







Basics of VHDL Execution Process (Concurrent and Sequential) 




In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach. Welcome to this beginner's guide on VHDL basics, where we will dive into the concepts of sequential and concurrent statements in VHDL. If you've ever been confused about these fundamental aspects of VHDL programming, this video is perfect for you. We will start by explaining the differences between sequential and concurrent statements, providing clear examples and illustrations to eliminate any confusion. By the end of this video, you will have a solid understanding of how to effectively utilize sequential and concurrent statements in your VHDL designs. This guide is suitable for beginners who have some basic knowledge of VHDL. We will go step-by-step and explain each concept thoroughly, ensuring that you grasp the fundamentals before moving on to more advanced topics. Make sure to subscribe to our channel for more informative videos on VHDL programming and digital design. Don't forget to hit the notification bell to stay updated with our latest uploads. If you have any questions or suggestions, feel free to leave them in the comments section below.

       Before start writing of codes in VHDL for digital systems you must know about the execution of VHDL language, you should know that how the tools process the VHDL code. This is a very important concept you should understand for proficiency in VHDL.

VHDL can be programmed in following execution pattern.
1.Concurrent Execution.
2.Sequential Execution.
 
 
VHDL can work on –
1.Concurrent Statements.
2.Sequential Statements.
3.Net-List Language.
4.Timing Specification.
5.Waveform Generation Language.
 
 
Sequential statements are very much like software languages. These statements execute sequentially that means at the start statement 1 will execute and then statement 2 will execute than statement 3 will execute and so on.

This means that sequential statements must be in correct order, just like the flow-charts we have in software.  Let’s understand this with a simple example.


If (a=b) then
    eq <= ‘1’;
Else
   eq <= ‘0’;
End if;

We also have the concurrent statements in VHDL, these statements are very likely to a hardware model like a schematic design. All the concurrent statements execute simultaneously, just like hardware. 

So if you have Concurrent statement 1 and statement 2 and 3 and 4 and so on… and all these statements executes concurrently, which means when the concurrent statement 1 is executing at the same time statement 4 is executing, similarly at the same time statement 2 or statement 3 are executing. I mean all are executing at the same time, so this is important to know that the sequence or order of the statements not really matter if your statement executing concurrently, and you can write them anywhere within the architecture without thinking of the sequence. And the results will be the same.




Net list language –
Net list language is also working on Concurrent execution. But only the difference is in net list language we design our system by defining the basic elements like gates or collection of gates (called modules and registers). 

** Above three languages are used for designing purpose.


Other two languages i.e. Timing specification and waveform generation language are used for verification purpose. In brief-
Timing Specification -  we can define the flow of data from input to output in our simulation screen but again this cannot be implemented in real life hardware because you can't specify the time of flow of data. So timing specification language only use in writing of test benches. Same a waveform generation language,
Is used for creation of waveforms, basically this is a  algorithm to get the same output by minimizing the processing time.


For more information you can go with our video tutorial series.

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Friday, November 8, 2013

VHDL/ FPGA Design Flow













Design Specification – Design specification is the state at which we define the important parameters like – consider a system / design of counter then specify start point, end point, length of counter, should have synchronous reset, reset is at logic high, at reset output should be ‘0’ etc.


Design specification include Market Requirement Documents (MRD Sheet), High Level Design, Low / Micro Level Design and RTL Coding Part.


Design specification process starts from the MRD Sheet (Market Requirement Documents), This outlines the requirements of a new product. This section covers the market needs, the customer value proposition, and product functionality. It is developed by the marketing team and upper level management.



High Level Design (HLD) -   At this state we defined all the major blocks of any complex system and also defines how they communicate or connected to each other like consider a microcontroller then the major block ay be RAM, ROM, Micro-Processor, Timer, Ports, ADC, Counters, etc.



Low Level Design (LLD) -  At this state we describes that how all major blocks of main system / design will be implement. It contains details of State Machines, Counters, MUX, Decoders, Internal registers etc. This phase need a lot of time to implement.



RTL Coding  -  At this stage we convert our micro design into HDL (VHDL / Verilog HDL) code using synthesizable constructs of language. This part consist of coding.

In real life RTL Code means that how the small modules and components are connected to each other or how data flows threw registers but in HDL language any code or collection of statements that are synthesizable are called RTL code.




Design Simulation  -  Simulation is the process of verifying the functional specification of system. We use simulators for simulation purpose. To test weather the RTL code meets the functional specification or not, we must see all the RTL block are functioning correctly with all the possibilities. For that purpose we use test benches. This takes 60 – 70 %of time in design verification. 

Design Simulation : Learn VHDL with Naresh Singh Dobal Series

Simulation are mainly two types.

First is Functional Simulation or Behavior Simulation – Functional simulation is the verification of functionality in the term of waveforms without considering timing specification.

Timing Simulation or SDF Simulation – Timing simulation also called Gate level simulation needs complete synthesis, place and route and timing details. In Timing simulation we consider all the timing and other parameters for real time simulation by considering delay of all Gate level netlist.



Synthesis -  Synthesis is the process in which synthesis tool like design compiler (Xilinx XST or vivado etc), take RTL in Verilog or VHDL, and convert that code into the Register Level Netlist according to target technology.

Design Synthesis : Learn VHDL with Naresh Singh Dobal Series.

Formal Verification – Check if the RTL to gate mapping is correct.

Scan Insertion – Insert the scan chain in case of ASIC.



Place & Route -  The gate – level netlist from the synthesis tool is taken and imported into place & route tool in verilog or vhdl netlist format, all the flip flops and gates are placed and routed according to place and route (PNR) tool, P&R tool generate GDS file used by foundry for ASIC Verification.

Configuration - This is the Implementation stage where we configure our FPGA Devices according to our requirement or RTL Structures. Now the configured device ready for real life testing and application use.



Post Sil. Validation – Once the chip is back from fabrication, It need to put in real environment for testing before sending it to market. Se we need post silicon validation step.




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