VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide] - Part ii

 

Click Here for Video Tutorial - VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide] - Part ii

This is the Part ii of last Video "VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]", for deeper understanding, and it is very important to have deeper insights on Sequential and Concurrent statement, if you are designing anything in VHDL or Verilog HDL. In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach. Now dig down little more with an example - Here I written two architectures with identical statements, top left architecture will execute those statements concurrently, but bottom right architecture will execute statements sequentially. Here if you noticed that in both the statements the output signal is same, that is Dout. And we are saying Dout gets the value of logical AND of inputs and in the second statement we says Dout gets the value of logical OR of inputs.

architecture Concurrent of my_design is begin Dout <= A AND B ; Dout <= A OR B; end Concurrent; --------------------------------------------- architecture Sequential of my_design is begin process (A,B,C) begin Dout <= A AND B ; Dout <= A OR B; end process; end Sequential;

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Do you see any problem in this structure ? If your answer is No, than try to figure out the output if input A is ‘0’ and input ‘B’ is 1, so the output of the AND gate is digital ‘0’ and the output of the OR gate is digital ‘1’, and you shorted them both these outputs. This is not good for the hardware, right? This is called contention, because two set of logics are driving the same signal and this is not allowed to synthesized as well, so You will not be able to synthesized your design, and you will probably get the synthesizer error in such cases. Now let’s talk about the sequential statements – Here we have the same set of statements, but these are now executing sequentially, means 1st statement executes first which says Output Dout gets the value of logical AND of inputs. So we made a AND gate. Now execute the 2nd statement which says Output Dout gets the value of logical OR of inputs. So here this second statement override the output signal Dout. Which means at the end of this statement Dout has the value of OR function. And the first statement of AND function get’s ignore completely. And we will get the only functionality of OR gate.

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VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]

 

Click here for Video Tutorial - VHDL Basics : Insights Sequential and Concurrent Statements - No More Confusion [Beginner’s Guide]

Before starting this, I wanted to give little weightage here, that This Concept is very important to understand if you are designing anything in the hardware description language. 

In the previous session, We were talking couple of times about the Sequential statements and Concurrent statements, and As we said VHDL supports both the executions. In this slide we will have little more understanding about those sequential statements and concurrent statement in VHDL.

Let’s take the same example, If you notice it is the same code we have used in our last session where we have 2 inputs, input A & input B and 1 output. We have one internal signal S as well. Where signal S was the output of a NAND gate and later that signal S wired up with the not gate and output of the NOT gate connected to the output Dout.

For this design We had written both type of statements in our VHDL code, which are concurrent statements and sequential statements.

Let’s explore the area where we used process and written some conditional statements like if-else, these statements inside the process executes sequentially, and hence called sequential statements in VHDL. The second area is where we written a statement outside the process, within the architecture, these statements will execute concurrently and hence called concurrent statements in VHDL. Likewise in this example, in VHDL we can write both type of statements which are sequential and concurrent statements to describe the functionality of our digital system.

Interesting part is, all the statements inside the process are sequential statements and executes sequentially but the process statement itself executes concurrently with other concurrent statements. Here, we have 2 concurrent statements 1 is very clear, I believe, and 2nd concurrent statement will be the whole process from start of process to end of process.

If you noticed we terminated the process statement at the end of process with the semicolon not in the line where we started our process, this means although there are multiple lines inside the process which are separately terminated but the process itself is only terminated where the process ends and hence it’s treated as single statement of concurrent statement. I know this may take little time to have deeper understanding, but we will be discussing lot more on this topic later to make this clear.

But first let's explore the difference between execution style of concurrent statements and sequential statements.

Sequential statements are very much like software languages. These statements execute sequentially that means at the start statement 1 will execute and then statement 2 will execute than statement 3 will execute and so on.

We also have the concurrent statements in VHDL, these statements are very likely to a hardware model like a schematic design. All the concurrent statements execute simultaneously, just like hardware. 

So if you have Concurrent statement 1 and statement 2 and 3 and 4 and so on… and all these statements executes concurrently, which means when the concurrent statement 1 is executing at the same time statement 4 is executing, similarly at the same time statement 2 or statement 3 are executing. I mean all are executing at the same time, so this is important to know that the sequence or order of the statements not really matter if your statement executing concurrently, and you can write them anywhere within the architecture without thinking of the sequence. And the results will be the same.

In this comprehensive tutorial, we will cover everything you need to know about VHDL sequential and concurrent statements. Sequential statements allow us to execute code in a step-by-step manner, while concurrent statements offer a more parallel execution approach. Welcome to this beginner's guide on VHDL basics, where we will dive into the concepts of sequential and concurrent statements in VHDL. If you've ever been confused about these fundamental aspects of VHDL programming, this video is perfect for you. We will start by explaining the differences between sequential and concurrent statements, providing clear examples and illustrations to eliminate any confusion. By the end of this video, you will have a solid understanding of how to effectively utilize sequential and concurrent statements in your VHDL designs. This guide is suitable for beginners who have some basic knowledge of VHDL. We will go step-by-step and explain each concept thoroughly, ensuring that you grasp the fundamentals before moving on to more advanced topics. Make sure to subscribe to our channel for more informative videos on VHDL programming and digital design. Don't forget to hit the notification bell to stay updated with our latest uploads. If you have any questions or suggestions, feel free to leave them in the comments section below.

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VHDL Tutorial : Signal Syntax - Short & Easy : No More Confusion - A Beginner’s Guide

 

Click here for Video Tutorial - VHDL Tutorial : Your First VHDL Design: VHDL Entity & Architecture - A Beginner's Guide

Today we will be learning, one of the important term in VHDL which you will use frequently in system designs, I am talking about the internal signals inside the module. You can treat them like interconnection between two logical units or wires in simple terms.

Till now, we were talking about the signals which are in the port list inside the entity description, that means we were defining the input or the output pin of our module, But think of the wires which interconnects inside our logical design and those we wanted to use inside our functional description to connect two elements. 

In VHDL terms we define them with the keyword “Signal” and these need to be defined inside the architecture.

The main difference between the port signals which we define in the entity and another which we are defining the architecture is that, Signals from the port list are the interface pins of your module as input or output, and can be used inside the architecture associated with that entity, but the signals which we define inside the architecture, are not actually the interface pins but we wanted to use them internally and these signals can only works inside that architecture.

In VHDL we do that by declaring the signals in the architecture between the architecture and begin statement as I am mentioning in the example.

In this example inside the Video, Look over the schematic where first we are doing a NAND function between input A and input B, than we are connecting the output of NAND gate to a NOT gate and the output of Not gate is our final output. Simple. Right.

Now look over the wire which is connecting the output of the NAND gate an input to the NOT gate, We call this interconnection or wire. And in terms of VHDL we are calling this signal.

Now if you noticed, this signal is neither the input interface of you module nor the output interface of your module but it is just laying inside the module.

So let’s declare the internal signal than,

We declare the internal Signal, named as S and defined it’s data type as BIT. After this declaration now we can use this signal S in our architecture anywhere and can connect different parts of our function.

Let’s explore little our code now, Here we have some sequential statements inside the process body, that if both the inputs, these are input A and input B are equal to 1 than our internal signal S will get the value of 0, and if any input is ‘0’ than our internal signal S will get the value ‘1’, 

Now if you had taken a note that this conditional statement acts simply like a NAND Gate and our internal signal S gets the function of NAND gate, and to get the function of AND gate in the output Dout, We inverted the signal S with a not gate and the output of the NOT gate is our final output Dout. And This output Dout is the output of our module.

So let me give a quick brief what we did here, We are designed a simple AND gate, that means Output Dout will be ‘1’ if both inputs are ‘1’ else the output Dout will be ‘0’ – 

So, First we defined the entity which has 2 inputs, input A and input B and 1 output Dout. 

Than we declared a signal inside the architecture which will act as a internal signal. And inside the process body, we write the behavior of a NAND gate, and moved the result into our internal signal S.

Now in the concurrent statement, outside the process we used the not gate to invert the value of internal signal S and than moved that to our final output Dout. Note that Dout is the output of our interface which we declared in the entity.

So that was the basic idea of HDL that we describe multiple behaviors and than wire them together using the internal signals.

At that moment, Don’t be confused with concurrent statement and sequential statement because we will be covering them later in this series, but just understand at the moment that anything which we are writing inside the process will execute sequentially and those statements which are outside the process body will execute concurrently. 

Welcome to VHDL Signal Syntax: A Short & Easy Guide for Beginners! If you've ever been confused about VHDL signal syntax, this video is perfect for you. Designed specifically for beginners, we'll cover all the essentials of VHDL signal syntax in a simple and straightforward manner. In this tutorial, we'll dive into VHDL and demystify the signal syntax, ensuring that you have a solid foundation to build upon. We'll walk you through the fundamental concepts, providing clear explanations and examples along the way. Whether you're new to VHDL or looking to brush up on your skills, this beginner's guide has got you covered. By the end, you'll have a clear understanding of VHDL signal syntax, enabling you to write efficient and error-free code. Here's what you'll learn: Introduction to VHDL signal syntax Syntax rules and guidelines for defining signals Signal declaration and assignment Types of signals and their usage Handling and manipulating signals in VHDL Real-world examples to reinforce your understanding If you're ready to unravel the mysteries of VHDL signal syntax, click play and let's get started!

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VHDL Tutorial : Your First VHDL Design: VHDL Entity & Architecture - A Beginner's Guide

 

Click here for Video Tutorial - VHDL Tutorial : Your First VHDL Design: VHDL Entity & Architecture - A Beginner's Guide

From our last videos of the playlist, once you have understanding of why we wanted to use a hardware description language like VHDL for designing our digital systems and FPGA or ASICs, we need to start with the basics of creating a VHDL design.

So today we will be creating a basic VHDL module, including the interface and Functional description.

You will be needing two main items for creating a design in VHDL.

First is to define all the inputs and outputs of the design. We call this interface of our module or digital system. So, we need to write VHDL code for all inputs and outputs of our digital system to tell the tool about the interface of our module.

The Second item we need to define the functionality of our digital system. So in this section you will write a VHDL code to define what you wanted to get from your digital system, and how it will be achieved. This can be the behavior definition from the sequential statements or the structure design or can be set of concurrent statements.

Once you complete these 2 basic needs, you will have a complete VHDL design for your digital system.

Let’s combine the entity unit and the architecture unit to get our complete VHDL design. 

This complete design has both the interface description as entity and the behavioral description as architecture and this complete component can be correctly synthesized and place and route into the FPGA.

We normally put both the entity unit and the architecture unit in the same file, and we prefer to put entity before the architecture for easy readability.

entity MUX is

port ( A : in bit ;

B : in bit ;

Sel : in bit ;

Dout : out bit) ;

end MUX;

architecture MUX_Design of MUX is

Begin

process (A,B,Sel)

begin

if (SEL=‘0') then

Dout <= A ;

else

Dout <= B ;

end if ;

end process ;

end MUX_Design ;

Welcome to the ultimate beginner's guide for Your First VHDL Design! In this video, we will dive into the fundamentals of VHDL Entity and Architecture and provide you with a comprehensive understanding of the topic. Whether you are new to VHDL or looking to refresh your knowledge, this guide is designed to help you get started and pave your way to becoming an expert VHDL designer. In this tutorial, we will cover the basics of VHDL, starting with the VHDL Entity and its crucial role in the design process. You will learn how to define and describe the inputs and outputs of your VHDL design using the Entity section, providing the necessary specifications for your project. Moving on, we will explore the VHDL Architecture, which defines the actual implementation of your design. Through a step-by-step walkthrough, you will discover how to construct the architecture block by block, ensuring a well-structured and functional VHDL design. To make the learning experience more practical, we will dive into real-world examples and demonstrate each concept using a popular VHDL software tool. You'll witness the transition from theory to practice, gaining hands-on experience in VHDL design. With this beginner's guide, you'll not only grasp the essentials of VHDL Entity and Architecture but also acquire the ability to kickstart your own VHDL designs, opening up a wide range of possibilities in digital circuit design. Subscribe to our channel for more exciting VHDL tutorials and stay tuned for upcoming videos in this series where we will explore advanced VHDL concepts and applications.

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VHDL - Language for Hardware Design : Begin the World of FPGA Design Tools & VHDL Design Flow

 

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Click Here for Video Tutorial :  VHDL - Language for Hardware Design :   Begin the World of FPGA Design Tools & VHDL Design Flow

Welcome to our comprehensive guide on FPGA design tools and VHDL design flow! In this video, we dive into the fascinating world of FPGA design and explore the essential tools and methodologies needed for successful FPGA development. Whether you're a beginner or an experienced engineer, this tutorial will provide valuable insights and tips to enhance your FPGA design skills. We start by introducing the fundamentals of FPGA design, explaining the benefits and versatility of using FPGAs in various applications. From there, we explore the wide range of design tools available, from popular industry-standard software like Xilinx Vivado and Altera Quartus Prime to open-source alternatives like GHDL and Icarus Verilog. We highlight the strengths and features of each toolset, enabling you to choose the most suitable one for your projects. With a solid foundation in FPGA design and tools, we then delve into the VHDL (VHSIC Hardware Description Language) design flow. From understanding the basics of VHDL syntax to implementing complex digital designs, we provide step-by-step explanations and practical demonstrations. You'll learn about entity and architecture design, the importance of libraries, and how to simulate and synthesize VHDL code for your FPGA. To ensure a holistic learning experience, we discuss common challenges and pitfalls in FPGA design and provide valuable troubleshooting tips. We also touch upon advanced topics like FPGA optimization techniques, timing analysis, and physical implementation considerations. So, whether you're a student, hobbyist, or professional looking to enhance your FPGA design skills, this tutorial is the ultimate resource to get started on your journey. Join us now and unlock the vast potential of FPGA design tools and the VHDL design flow! FPGA design tools, VHDL design flow, FPGA development, Xilinx Vivado, Altera Quartus Prime, VHDL, Verilog, VHDL syntax, digital design, entity architecture, libraries, simulate VHDL code, synthesize VHDL code, FPGA optimization techniques, timing analysis, physical implementation, FPGA design skills.

Don't miss out on this VHDL revolution! Join us today and unlock endless possibilities in the realm of digital design. Subscribe to our channel for more exciting tutorials and stay ahead in the ever-evolving world of technology.

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VHDL - Language for Hardware Design : Don’t Miss Out On The VHDL Revolution- Learn It Today!

 Click Here for Video Tutorial - VHDL - Language for Hardware Design :   Don’t Miss Out On The VHDL Revolution-Learn It Today!

 Click Here for Video Tutorial - VHDL - Language for Hardware Design :   Don’t Miss Out On The VHDL Revolution-Learn It Today!

VHDL - Language for Hardware Design : Don’t Miss Out On The VHDL Revolution - Learn It Today! Are you fascinated by the world of digital design? Interested in learning the powerful hardware description language, VHDL? Look no further! In this comprehensive beginner's guide, we bring you an opportunity to embark on a journey to master VHDL and join the revolution of digital design. VHDL (VHSIC Hardware Description Language) serves as a crucial tool for designing and describing digital systems. Whether you are an aspiring engineer, a student, or a professional seeking to enhance your skill set, this tutorial will provide you with a solid foundation in VHDL. Throughout this video series, we delve into the fundamentals of VHDL, explaining its syntax, data types, operators, and control structures. We'll explore various modeling techniques, such as data flow and behavioral modeling, enabling you to conceptualize complex digital circuits effortlessly. You'll also gain insights into designing finite state machines (FSMs) and understanding the importance of testbenches for verification. To make your learning experience interactive and engaging, we offer practical examples and guide you through hands-on projects. By the end of this tutorial, you'll be equipped with the knowledge and confidence to design your digital systems using VHDL. Don't miss out on this VHDL revolution! Join us today and unlock endless possibilities in the realm of digital design. Subscribe to our channel for more exciting tutorials and stay ahead in the ever-evolving world of technology.

Subscribe to Learn and Grow Community for Regular updates. Subscribe to our community for more informative videos and guidance. Stay tuned for tutorials, tips, and tricks to enhance your skills. Hit the notification bell to never miss an update.

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We're excited to announce that we're launching Learn and Grow Community, a community of learners who are passionate about skill development and growth. and Peoples Who believes that Learning and self-improvement or skill up yourself is the key to grow in life and career in the long way, than Subscribe "Learn and Grow Community" today (youtube.com\@learnandgrowcommunity) and be a part of the learn and Grow Community!

VHDL - Language for Hardware Design : Know why you need to learn VHDL?

Click Here for Video Tutorial - VHDL - Language for Hardware Design : Know why you need to learn VHDL?

Click Here for Video Tutorial - VHDL - Language for Hardware Design : Know why you need to learn VHDL?

What is VHDL? VHDL, short for Very High-Speed Integrated Circuit Hardware Description Language, is a powerful and widely used language for designing digital circuits and systems. If you're interested in digital electronics or pursuing a career in hardware design, learning VHDL is essential. Why Learn VHDL? Understanding VHDL gives you the ability to design and simulate complex digital systems, ranging from simple logic gates to advanced processors. VHDL allows you to describe the behavior and structure of these circuits accurately, enabling efficient development and debugging. By learning VHDL, you gain the skills to create efficient and reliable hardware designs. How to Learn VHDL? Learning VHDL doesn't have to be intimidating! In this tutorial video, we will guide you through the basics of VHDL, explaining the syntax, data types, and essential concepts. We'll also provide practical examples and hands-on exercises to reinforce your understanding. Whether you're a beginner or have some experience with digital design, this video will help you grasp VHDL quickly. Join Our VHDL Community Connect with fellow VHDL enthusiasts and learners in our vibrant community. Share ideas, ask questions, and collaborate with others passionate about hardware design. Our community is a supportive and engaging space to expand your knowledge and stay updated with the latest VHDL developments. Subscribe to Learn and Grow Community for Regular updates. Subscribe to our community for more informative videos and guidance. Stay tuned for tutorials, tips, and tricks to enhance your skills. Hit the notification bell to never miss an update.

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Video Learning Series : Interfacing LED & Switch ::: Task - 3 with Codes & Video

 Video Learning Series : Interfacing LED & Switch ::: Task - 3

Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)

Video Link -
https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q


TASK 3  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. -
Description -    LED's Starts Blinking when Switch is pressed & Remains same as it's last update when Switch is released.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sl3 is
port (clk : in std_logic;
din : in std_logic;
dout : out std_logic_vector (7 downto 0));
end sl3;

architecture sl2_arc of sl3 is
begin
    p0 : process (clk,din) is
    variable m : std_logic_vector (24 downto 0) := (others=>'0');
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        if (din='0') then
            case m(24) is
                when '0' => dout <= "00000000";
                when others => dout <= "11111111";
            end case;
        end if;
    end process p0;
       
end sl2_arc;




Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below

Best Regard //

Naresh Singh Dobal

nsdobal@gmail.com

Video Learning Series : Interfacing LED & Switch ::: Task - 2 with Codes & Video

 Video Learning Series : Interfacing LED & Switch ::: Task - 2

 

 

 

Click Here For Video  ::: Video Learning Series (vhdlbynaresh.blogspot.com)

Video Link  -
https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q


 TASK 2  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. -
Description -    LED's Starts Blinking when Switch is pressed & goes OFF when Switch is released.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sl2 is
port (clk : in std_logic;
din : in std_logic;
dout : out std_logic_vector (7 downto 0));
end sl2;

architecture sl2_arc of sl2 is  --frequncy is 50 MHz
begin
    p0 : process (clk,din) is
    variable m : std_logic_vector (24 downto 0) := (others=>'0');
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        if (din='0') then
            case m(24) is
                when '0' => dout <= "00000000";
                when others => dout <= "11111111";
            end case;
        else
            dout <= (others => '0');
        end if;
    end process p0;
       
end sl2_arc;


 Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below

Best Regard //

Naresh Singh Dobal

nsdobal@gmail.com

Video Learning Series : Interfacing LED & Switch ::: Task - 1 with Codes & Video

Video Learning Series : Interfacing LED & Switch  :::  Task - 1

Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)

Video Link  - 
https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q


 TASK 1  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. - 
Description -    LED goes  ON when Logic 1 is given by switch as input & goes OFF when Logic '0' is given by switch as input.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -  

library ieee;
use ieee.std_logic_1164.all;

entity sl1 is
port (din : in std_logic ;
dout : out std_logic_vector (7 downto 0));
end sl1;

architecture sl1_arc of sl1 is
begin

dout <= "00000000" when din='0' else
"11111111";

end sl1_arc;



Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below

Best Regard //

Naresh Singh Dobal

nsdobal@gmail.com

VHDL Lab Exercises...

VHDL Lab Exercise...

Learn VHDL with Naresh Singh Dobal Test Series...

1.  LAB Exercise 1             (Combinational System Design using Gates).

2.  LAB Exercise 2             (Combinational System Design data flow).

3.  LAB Exercise 3             (Combinational System Design using Behavior Model).

4.  LAB Exercise 4             (Flip Flop & Latches Design using Behavior Model).

5.  LAB Exercise 5             (Counters & Frequency Dividers Design using Behavior Model).

6.  LAB Exercise 6             (Hardware Peripherals &  System Design using Behavior Model).

7.  LAB Exercise 7             (Combinational System Design using Structural Model).

8.  LAB Exercise 8             (Flip Flop & Shift register design using Structural Model).



I also linked Solutions for most of the assignment

If you feel any difficulties in any assignment then you can follow the links mentioned in the last of assignment pages...

I would love to read your suggestions and comments here below.

My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 8

VHDL Lab Exercise   :::   Exercise 8

LAB- 8  DESIGN OF SHIFT REGISTERS AND FLIP-FLOPS USING STRUCTURAL MODEL.

VHDL Lab Exercise 8 :: VHDL with Naresh Singh Dobal Learning Series.

If you feel any difficulties in any assignment then follow the below link...

Solutions for problems in System Design.

I would love to read your suggestions and comments here below.

My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 7

VHDL Lab Exercise   :::   Exercise 7

LAB5  COMBINATIONAL SYSTEM DESIGN USING STRUCTURAL MODEL.

VHDL Lab Exercise 7 :: VHDL with Naresh Singh Dobal Learning Series.

If you feel any difficulties in any assignment then follow the below link...

Solutions for problems in System Design.

I would love to read your suggestions and comments here below.

My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com