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Tuesday, November 19, 2013

VHDL Lab Exercises...






VHDL Lab Exercise...

Learn VHDL with Naresh Singh Dobal Test Series...



1.  LAB Exercise 1             (Combinational System Design using Gates).

2.  LAB Exercise 2             (Combinational System Design data flow).

3.  LAB Exercise 3             (Combinational System Design using Behavior Model).

4.  LAB Exercise 4             (Flip Flop & Latches Design using Behavior Model).

5.  LAB Exercise 5             (Counters & Frequency Dividers Design using Behavior Model).

6.  LAB Exercise 6             (Hardware Peripherals &  System Design using Behavior Model).

7.  LAB Exercise 7             (Combinational System Design using Structural Model).

8.  LAB Exercise 8             (Flip Flop & Shift register design using Structural Model).



I also linked Solutions for most of the assignment
If you feel any difficulties in any assignment then you can follow the links mentioned in the last of assignment pages...


I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

2 comments:

  1. Can you provide a structural domain programming of this 8x1 Mux
    mail to amitkumarececu@ygmail.com if possible

    ReplyDelete