Tuesday, 16 July 2013

How to write Codes in Structural Modeling Style in VHDL






Syntax -

Component Declaration -


COMPONENT  component_name  IS
        PORT (     
                    List of Interface Ports
                   );
END COMPONENT Component_name; 


Sample -

component     component_name
       port    (port_signal_names :    mode    type ;
                   port_signal_names :    mode    type ;
                    .
                    .
                    port_signal_names :    mode    type );
end component
                            



Component Instantiation -

Component_label    :     Instance_name    PORT MAP    (Association-list) ;


  • Component_label can be any legal identifier and considered as the name of the instance.
  • Instance_name must be the name of a component declared earlier using a component declaration.


Methods of Component Instantiations -

  • Positional Mapping.
  • Nominal Mapping.


Positional Mapping. -   

Example -

u0 : dff       PORT MAP    (clk  ,   reset    ,   din   ,    dout );

Sequence of Formal ports must be same with sequence of Actual Ports of component.



Nominal Mapping -

Example -

u0 : dff      PORT MAP     ( clk  =>  clk   ,  
                                            reset   =>   reset    ,
                                             din   =>   din,
                                                  dout   =>   dout )   ;


No need to consider the sequence of Formal ports and Actual Ports.



 Sample Programs-


Flip Flop Design using Structural Modeling Style-

Shift Registers Design using Structural Modeling Style-

  • 4 - Bit Stack Design using Structural Modeling Style (VHDL Code).
  • 4 - Bit Queue Design using Structural Modeling Style (VHDL Code).

 

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