Wednesday, 17 July 2013

Design of Serial IN - Serial Out Shift Register using D-Flip Flop (VHDL Code).





Design of Serial IN -  Serial OUT   Shift Register using D-Flip Flop (Structural Modeling Style).


Output Waveform :   Serial IN   Serial OUT  Shift Register


VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : siso
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of 4 Bit Serial In - Serial Out Shift Register using D_Flip flop.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity siso is
     port(
         din : in STD_LOGIC;
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end siso;

architecture siso_arc of siso is  

component d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component d_flip_flop;

signal s : std_logic_vector(2 downto 0);

begin       
   
    u0 : d_flip_flop port map (clk => clk,
    din => din,
    reset => reset,
    dout => s(0));
   
    u1 : d_flip_flop port map (clk => clk,
    din => s(0),
    reset => reset,
    dout => s(1));
   
    u2 : d_flip_flop port map (clk => clk,
    din => s(1),
    reset => reset,
    dout => s(2));
   
    u3 : d_flip_flop port map (clk => clk,
    din => s(2),
    reset => reset,
    dout => dout);   
   

end siso_arc;



-------------------- D Flip Flop Design ---------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is   

begin
   
    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;


end d_flip_flop_arc;

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