Monday, 15 July 2013

Design of 8 : 1 Multiplexer Using When-Else Statement (VHDL Code).

Design of 8 : 1 Multiplexer Using When-Else Concurrent Statement (Data Flow Modeling Style)-


Output Waveform : 8 : 1 Multiplexer


VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : multiplexer8_1
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 8 : 1 multiplexer using when else.vhd

   
   
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer8_1 is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         sel : in STD_LOGIC_VECTOR(2 downto 0);
         dout : out STD_LOGIC
         );
end multiplexer8_1;

architecture multiplexer8_1_arc of multiplexer8_1 is
begin
  
    dout <= din(7) when (sel="000") else
            din(6) when (sel="001") else
            din(5) when (sel="010") else
            din(4) when (sel="011") else
            din(3) when (sel="100") else
            din(2) when (sel="101") else
            din(1) when (sel="110") else
            din(0);

end multiplexer8_1_arc;

6 comments :

Anonymous said...

Can you provide a structural domain programming of this 8x1 Mux
mail to saurabh_pati@yahoo.com if possible

Anonymous said...

thank you... :)

amit kumar said...
This comment has been removed by the author.
amit kumar said...

Can you provide a structural domain programming of this 8x1 Mux
mail to amitkumarececu@gmail.com if possible

satya narayana said...

Can you provide a structural domain programming of this 8x1 Mux
mail to satyanarayana1456@gmail.com

Anonymous said...

Plz provide test bench file for this pgm....

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