Tuesday, 16 July 2013

Design of 4 Bit Adder using 4 Full Adder - (Structural Modeling Style) (VHDL Code).





Design of 4 Bit Adder using 4 Full Adder (Structural Modeling Style)-




Output Waveform :   4 Bit Adder using 4 Full Adder




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : adder_4bit
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 4 Bit Adder using Structural Modeling Style.vhd




library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         carry : out STD_LOGIC;
         sum : out STD_LOGIC_VECTOR(3 downto 0)
         );
end adder_4bit;

architecture adder_4bit_arc of adder_4bit is

Component fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end component;       

signal s : std_logic_vector (2 downto 0);

begin
   
    u0 : fa port map (a(0),b(0),'0',sum(0),s(0));
    u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
    u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
    ue : fa port map (a(3),b(3),s(2),sum(3),carry);

end adder_4bit_arc;           







---------------- Full Adder Design ----------------------







library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fa is
    port (a : in STD_LOGIC;
          b : in STD_LOGIC;
          c : in STD_LOGIC;
          sum : out STD_LOGIC;
          carry : out STD_LOGIC
          );
end fa;

architecture fa_arc of fa is
begin
   
    sum <= a xor b xor c;
    carry <= (a and b) or (b and c) or (c and a);
   
end fa_arc;

6 comments :

Anonymous said...

I am working on this code for a 4 bit adder. I tried to compile the code but it stated there " Error : Node instance "u0" instantiates undefined entity "fa"...How do I solve this? Help me please. Thank You.

Bhavesh Sethi said...

I have an assignment which contains the following 2 questions:
1. Design 4 bit adder using macro of full adder
2. Design 4 bit adder using structural modelling

What is the difference between the two??

Anonymous said...

No Difference

Unknown said...

test bench?

Anonymous said...

can you share the verilog code?

Anonymous said...

behen ke lode maadarchodo...aesi cheezen bnata kon hai...fudi k kaam ni hota kuch....samajh ni aata koi prgrm..ghnta ni aata smjh

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