4 to 1 Multiplexer Design using Logical Expression (VHDL Code).

Data Flow Modelling Style : 4 to 1 Multiplexer Design using Logical Expression-

Output Waveform for 4 : 1 Multiplexer

Program-

-------------------------------------------------------------------------------
--
-- Title       : multiplexer_4_1
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer_4_1 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : in STD_LOGIC;
         d : in STD_LOGIC;
         x : in STD_LOGIC;
         y : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end multiplexer_4_1;

architecture multiplexer_4_1_arc of multiplexer_4_1 is
begin

    dout <= ((not x) and (not y) and a) or
            ((not x) and y and b) or
            (x and (not y) and c) or
            (x and y and d);

end multiplexer_4_1_arc;